• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    A semiconductor wafer includes first and second superlattice layers. The first superlattice layer includes the first unit layer each of which includes first and second layers, the second superlattice layer includes second unit layers each of which includes third and fourth layers, the first layer is formed of AlxiGa1_x1N (0 <x1~1), the second one Layer is formed of Aly1Ga1_y1N (0 ~ y1 <1, x1> y1), the third layer consists of Alx2Ga1-x2N (0 <x2 ~ 1), the fourth layer consists of Aly2Ga1_y2N (0 ~ y2 <1, x2> y2) , an average lattice constant of the first superlattice layer is different from that of the second superlattice layer, and one or more layers selected from the first and second superlattice layers contain impurities that improve the breakdown voltage and have a concentration of more than 7 × 10 18 [atoms / cm 3]. exhibit.
    公开号:AT521082A2
    申请号:T9292/2014
    申请日:2014-07-29
    公开日:2019-10-15
    发明作者:Sazawa Hiroyuki
    申请人:Sumitomo Chemical Co；
    IPC主号:
    专利说明:

    Technical Field The present invention relates to a semiconductor wafer and a method of manufacturing a semiconductor wafer.
    Background Art Methods for forming high quality nitride semiconductor crystal layers on silicon wafers for use with high breakdown voltage devices are desired. The non-patent document 1 discloses a structure in which a buffer layer, an over-lattice structure and a gallium nitride layer are arranged in the indicated order on the silicon (III) plane. Here, the gallium nitride layer provides an active layer of a transistor. This structure can achieve reduced warpage of the wafer by the presence of the superlattice structure and is thus advantageous in that a relatively thick gallium nitride layer can be easily formed and a high breakdown voltage nitride semiconductor crystal layer can be easily obtained. However, as the nitride semiconductor crystal layer is made thicker to increase the breakdown voltage, the warpage of the wafer increases and may exceed the potential range of distortion for the device fabrication step. The methods disclosed in Patent Documents 1 and 2 are known for controlling the amount of warpage of the wafer.
    According to the method disclosed in Patent Document 1, a first GaN / AlN superlattice layer is formed on a wafer. In the first GaN / AlN superlattice layer, several pairs of a GaN layer and an A1N layer are stacked on top of each other such that the GaN layers and the A1N layers are alternately stacked. In addition, a second GaN / AlN superlattice layer is formed and is in contact with the first GaN / AlN superlattice layer. In the second GaN / AlN superlattice layer, several pairs of a GaN layer and an A1N layer are stacked on top of each other such that the GaN layers and the A1N layers are alternately stacked. On the second GaN / AlN superlattice layer, a layer becomes / 33
    Operation of the device formed by a GaN electron transport layer and an AlGaN electron supply layer formed. Here, Patent Literature 1 discloses that the relationship LC1 <LC2 <LC3 is satisfied, where LC1 is the average lattice constant of the C-axis of the first GaN / AlN superlattice layer, LC2 is the mean lattice constant of the C-axis of the second GaN / AlN superlattice layer, and LC3 is the mean lattice constant of the C-axis of the GaN electron transport layer.
    Patent document 2 discloses an epitaxial wafer in which a series of Group III nitride films are formed on the (111) monocrystalline Si wafer such that the (0001) crystal plane is substantially parallel to the surface of the wafer. The epitaxial wafer includes a buffer layer and a crystal layer formed on the buffer layer, and the buffer layer is formed by alternately superposing the first units of the superimposing and second units of superposing such that the upper and lower portions are both defined by the first units of superimposing be formed. The first unit of superimposition includes a layer of compositional change and a first intermediate layer. In the layer of composition change, first unit layers and second unit layers having different compositions are repeated and alternately superimposed so that compressive stress is trapped therein. The first intermediate layer increases the compressive stress included in the layer of compositional change. The second unit of superimposition is formed as a second intermediate layer without substantial tension.
    [Prior Art Documents] [Patent Documents]
    Patent Document 1: Japanese Patent Application Publication No. 2011-238685 Patent Document 2: International Publication No. WO 2011/102045 [Non-Patent Document]
    Non-Patent Document 1: "High quality GaN grown on Si (III) by gas source molecular beam epitaxy with ammonia", S.A. Nikishin et al., Applied Physics letter, Vol. 75, 2073 (1999) / 33
    Disclosure of the invention
    Problems to be Solved by the Invention In order to obtain a high breakdown voltage nitride semiconductor crystal layer, the present inventors have made experiments and checked the results of introducing foreign atoms such as carbon atoms into a carrier layer (a superlattice layer) of the nitride semiconductor crystal layer. The present inventors have confirmed the above-mentioned approximation that simple imports of impurities have problems. More specifically, the stress in the superlattice layer, which is provided to control the amount of warpage of the wafer, is relaxed, and its effect of controlling the amount of warpage of the wafer is undermined. In other words, the present inventors have concluded the following. The method of controlling the amount of distortion of the wafer disclosed in the above-mentioned patent documents 1 and 2 can be used only when no impurities have been introduced to improve the breakdown voltage or when only a small amount of impurities have been introduced. The methods disclosed in Patent Documents 1 and 2 can no longer control the amount of distortion of the wafer when introducing foreign atoms to such an extent that the breakdown voltage is significantly improved.
    The objects of the present invention are to provide a semiconductor wafer having such a layer structure that the superlattice layer serving as a carrier layer of the nitride semiconductor crystal layer retains its effects of controlling the amount of distortion even if the superlattice layer has such an amount was doped to impurities that the breakdown voltage is effective and sufficiently improved, and to provide a method for producing the semiconductor wafer.
    Means for Solving the Problems In order to achieve the above-mentioned objects, a first embodiment of the present invention is to provide a semiconductor wafer comprising a carrier wafer, a first superlattice layer, a junction layer, a second superlattice layer, and a nitride semiconductor crystal layer. Here, the carrier wafer, the first superlattice layer, the interconnection layer, the second superlattice layer and the nitride semiconductor crystal layer are arranged in an order of the carrier wafer, the first superlattice layer, the interconnection layer, the second superlattice layer and the nitride semiconductor crystal layer, the first superlattice layer having a plurality of first unit layers each of which consists of a first / 33 ·· ·· ·· ·· ······················································································· ············································
    Layer and a second layer is constructed, the second superlattice layer a plurality of second
    Includes unit layers, each of a third layer and a fourth
    Layer is formed, the first layer of Al x iGai_ x iN (0 <xl <1) is formed, the second
    Layer of Al y iGai. y iN (0 <yl <1, xl> yl) is formed, the third layer of Al X 2Gai. X 2N (0 < x 2 <1), the fourth layer consists of Al j G Gaj ^ N (0 <y 2 <1, x 2> y 2), an average lattice constant of the first superlattice layer is different from a mean lattice constant of the second superlattice layer, one or more layers selected from the first superlattice layer and the second superlattice layer contain foreign atoms having an 18
    Improve breakdown voltage and have a concentration of more than 7 x 10 [atoms / cm].
    The foreign atoms may be one or more species selected from the group consisting of C atoms, Fe atoms, Mn atoms, Mg atoms, V atoms, Cr atoms, Be atoms and B atoms. The foreign atoms are preferably C atoms or Fe atoms. The bonding layer is preferably a crystal layer in contact with the first superlattice layer and the second superlattice layer. A compound layer composition may change continuously in a thickness direction of the interconnection layer from the first superlattice layer to the second superlattice layer. In another embodiment, a composition of the bonding layer may change stepwise in a thickness direction of the bonding layer from the first superlattice layer to the second superlattice layer. The bonding layer may be made of Al z Gai_ z N (0 <z <1). The thickness of the bonding layer is preferably larger than a thickness of each of the first layer, the second layer, the third layer, and the fourth layer. A mean lattice constant of the tie layer is preferably less than an average lattice constant of each of the first superlattice layer and the second superlattice layer.
    A second embodiment of the present invention is to provide a method of manufacturing the semiconductor wafer of the first embodiment. The manufacturing method includes forming the first superlattice layer by forming the first unit layer composed of the first layer and the second layer, forming the interconnection layer, forming the second superlattice layer by forming the second unit layer, which consists of the third layer and the fourth layer, and forming the nitride semiconductor crystal layer. Here, during one-or multiple-forming, one selected from forming the first superlattice layer and forming / 33
    44 44 44 4444 44 • 4 4 4 4 r 4 4 4 4 · • 4 4 4 4 A4 444 4 ·· · · 4 4 4 4 4 44 4 • 44 44 44 44 44 4 the second superlattice layer containing one or more the first superlattice layer and the second superlattice layer are formed to contain impurities which improve a breakdown voltage of the one or more of the first superlattice layer and the second superlattice layer and have a concentration of more than 7 x 10 [atoms / cm].
    Depending on a composition and the thickness of the nitride semiconductor crystal layer, one or more parameters selected from (i) a composition of each of the first to fourth layers, (ii) a thickness of each of the first to fourth layers, (iii) the number n the unit layers contained in the first superlattice layer and (iv) the number m of the unit layers included in the second superlattice layer are adjusted so that the warpage of the semiconductor wafer measured at a surface of the nitride semiconductor crystal layer is 50 pm or less. Depending on the composition and the thickness of the nitride semiconductor crystal layer, the number n of the unit layers contained in the first superlattice layer and the number m of the unit layers contained in the second superlattice layer are preferably set so that the warpage of the semiconductor wafer , measured at the surface of the nitride semiconductor crystal layer, is 50 pm or less.
    Brief Description of the Drawings FIG. 1 is a cross-sectional view of a semiconductor wafer 100.
    Fig. 2 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for semiconductor wafers of the first embodiment.
    Fig. 3 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for semiconductor wafers of the first comparative example.
    4 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for semiconductor wafers of the second comparative example.
    / 33
    Fig. 5 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for semiconductor wafers of the third comparative example.
    Fig. 6 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for semiconductor wafers of the second embodiment.
    Fig. 7 is a graph showing the amount of distortion with respect to the concentration of carbon atoms for semiconductor wafers of the first and second embodiments and the first to third comparative examples.
    Fig. 8 is a graph showing the amount of distortion and the breakdown voltage for semiconductor wafers of a third embodiment in which the numbers of the unit layers for the first and second superlattice layers are set to different values.
    Fig. 9 is a graph showing the amount of distortion for semiconductor wafers of a fourth embodiment in which the numbers of the unit layers of the first and second superlattice layers are set to different values.
    Fig. 10 is a graph showing the amount of distortion with respect to the average lattice constant difference for semiconductor wafers of a fifth embodiment.
    Best Mode for Carrying Out the Invention Fig. 1 is a cross-sectional view of a semiconductor wafer 100 according to an embodiment of the present invention. The semiconductor wafer 100 includes a carrier wafer 102, a buffer layer 104, a first superlattice layer 110, a connection layer 120, a second superlattice layer 130, and a nitride semiconductor crystal layer 140. The carrier wafer 102, the first superlattice layer 110, the interconnection layer 120, the second superlattice layer 130, and the nitride semiconductor crystal layer 140 are deposited in the order of the carrier wafer 102, the first superlattice layer 110, the interconnection layer 120, the second superlattice layer 130, and the nitride semiconductor crystal layer 140.
    The carrier wafer 102 is a carrier for applying the buffer layer 104 and the respective layers thereon, which will be described later. The carrier wafer 102 may be made of any material as long as the carrier wafer 102 has the mechanical strength required to deposit the individual layers and thermal stability that allows the individual layers to be formed by epitaxial growth and other methods. The carrier wafer 102 may be, for example, an Si wafer, a blue corundum wafer, a Ge wafer, a GaAs wafer, an InP wafer, or a ZnO wafer.
    The buffer layer 104 is designed to absorb the difference in lattice constant between the carrier wafer 102 and the first superlattice layer 110. The buffer layer 104 may be formed by epitaxial growth, with the reaction temperature (the temperature of the wafer) being set at 500 ° C to 1000 ° C. When an Si (11) wafer is used as the carrier wafer 102, and an AlGaN-based substance is used for the first superlattice layer 110, the buffer layer 104 may be, for example, an AlN layer. The buffer layer 104 preferably has a thickness of 10 nm to 300 nm, more preferably 50 nm to 200 nm.
    The first superlattice layer 110, the interconnection layer 120, and the second superlattice layer 130 provide a layered structure that allows the amount of distortion of the semiconductor wafer 100 to be restrained even when a sufficient amount of impurity atoms has been introduced to improve the breakdown voltage , The first superlattice layer 110 has a plurality of first unit layers 116, and the second superlattice layer 130 has a plurality of second unit layers 136.
    The first unit layer 116 is constructed by a first layer 112 and a second layer 114, and the second unit layer 136 is constructed by a third layer 132 and a fourth layer 134. The first layer 112 is made of Al x iGai. x iN (0 <xl <1), and the second layer 114 is made of Al y iGai. y iN (0 <yl <1, xl> yl) is formed. The third layer 132 is made of Al X 2Gai. X 2N (0 <x2 <1), and the fourth layer consists of Alj ^ Gai.j ^ N (0 <y2 <1, x2> y2).
    The first layer 112, the second layer 114, the third layer 132 and the fourth layer 134 may be formed by epitaxial growth. The first layer 112/33
    For example, the third layer 132 may be an A1N layer when x1 and x2 are set to 1. The first layer 112 and the third layer 132 preferably have a thickness of 1 nm to 10 nm, more preferably 3 nm to 7 nm. With respect to the second layer 114 and the fourth layer 134, y1 and y2 can be set in a range of 0.05 to 0.25. In other words, the second layer 114 and the fourth layer 134 may be Alo, o5Gao, 95N to Alo ^ sGaojsN, for example. The second layer 114 and the fourth layer 134 preferably have a thickness in the range of 10 nm to 30 nm, more preferably 15 nm to 25 nm.
    A plurality of first unit layers, each composed of a first layer 112 and a second layer 114, form the first superlattice layer 110. The average lattice constant of the first superlattice layer 110 can be determined by varying the compositions (the Al ratios) and the Thicknesses of the first layers 112 and the second layers 114 can be varied. The average lattice constant α 1 of the first lattice layer 110 may be defined as the result of the lattice constant of the first layers 112 x the ratio of the first layers 112 + of the lattice constant of the second layers 114 x the ratio of the second layers 114. The number n of the first unit layers 116 included in the first superlattice layer 110 is preferably in the range of 1 to 200, more preferably 1 to 150.
    A plurality of second unit layers 136, each constituted by the third layer 132 and the fourth layer 134, form the second superlattice layer 130. The average lattice constant a2 of the second superlattice layer 130 can be obtained by varying the compositions (the Al ratios) and the Thicknesses of the third layers 132 and the fourth layers 134 are varied. The mean lattice constant a2 of the second superlattice layer 130 may be defined as the result of the lattice constant of the third layers 132 x the ratio of the third layers 132 + the lattice constant of the fourth layers 134 x the ratio of the fourth layers. The number m of the second unit layers 136 contained in the second superlattice layer 130 is preferably in the range of 1 to 200, more preferably 1 to 150.
    In the semiconductor wafer 100, the mean lattice constant a1 of the first superlattice layer 110 is different from the mean lattice constant a2 of the second superlattice layer 130, and one or more layers selected from the first / 33.
    3 ··.
    • · · · ·
    Superlattice layer 110 and second superlattice layer 130 contain impurities that are set to increase the breakdown voltage and have a concentration of more than 7 x 10 18 [atoms / cm 3 ]. The foreign atoms may be one or more species selected from the group consisting of C atoms, Fe atoms, Mn atoms, Mg atoms, V atoms, Cr atoms, Be atoms and B atoms. The foreign atoms are preferably C atoms or Fe atoms, in particular C atoms.
    The connection layer 120 is formed so as to connect the first superlattice layer 110 and the second superlattice layer 130 to each other. The bonding layer 120 may be formed by epitaxial growth. The bonding layer 120 may, for example, made of Al z Gai_ z N (0 <z <1) are formed. The connection layer 120 may be a crystal layer in contact with the first superlattice layer 110 and the second superlattice layer 130. The tie layer may consist of a single or multiple layers. In addition, the composition of the bonding layer 120 may change in the thickness direction. Specifically, the composition of the interconnect layer 120 may continuously change in the thickness direction of the interconnect layer 120 from the first superlattice layer 110 to the second superlattice layer 130. In another embodiment, the composition of the interconnect layer 120 may change stepwise in the thickness direction of the interconnect layer 120 from the first superlattice layer 110 to the second superlattice layer 130. The thickness of the interconnect layer 120 may be set greater than the thickness of each of the first layer 112, the second layer 114, the third layer 132, and the fourth layer 134. The average lattice constant of the connection layer may be set smaller than the average lattice constant of each of the first superlattice layer 110 and the second superlattice layer 130. The thickness of the bonding layer 120 may be 20 to 300 nm, preferably 25 to 200 nm, more preferably 30 to 200 nm, particularly preferably 30 to 150 nm.
    The nitride semiconductor crystal layer 140 may include a base layer of the device 142 and an active layer 144. An increase in the thickness of the base layer of device 142 may result in a higher breakdown voltage of a device. In the active layer 144, an active region of a transistor, such as a channel, is formed.
    According to the semiconductor wafer 100 of the present embodiment, high breakdown voltage of 450 V or higher can be obtained by introducing impurities with a / 33
    Concentration of more than 7 x 10 18 [atoms / cm 3 ] can be realized, and at the same time, the amount of distortion measured on the surface of the nitride semiconductor crystal layer 140 can be reduced to 50 gm (the absolute value) or less. Here, the amount of distortion means the height of the center of the wafer with respect to the edge of the wafer, and assumes a negative value when the nitride semiconductor crystal layer 140 becomes convex and a positive value when the nitride semiconductor crystal layer 140 becomes concave.
    As mentioned above, even if the introduced impurities reach a concentration of 7 × 10 18 [atoms / cm 3 ], the amount of warpage of the semiconductor wafer 100 can be set to 50 gm or less (the absolute value) high breakdown voltage of 450 V or higher. This advantageous effect can be effected by the following mechanism.
    When a GaN-based crystal layer is placed on a Si wafer, the GaN-based crystal is lattice-grown on the Si wafer at a high temperature and warped upwardly concaved after the temperature is lowered because of the thermal expansion coefficient of the GaN-based crystal is higher than the thermal expansion coefficient of Si. When the GaN-based crystal layer is concaved upward, the surface of the GaN-based crystal layer opposite to the Si wafer is concave. Here, a laminate of an upper superlattice layer (USL) and a lower superlattice layer (LSL) is provided between the Si wafer and the GaN layer. The mean lattice constant a u of the USL layer and the mean lattice constant aL of the LSL layer are configured such that the relationship a u > aL is satisfied. In this way, the stress resulting from the difference in average lattice constant between the USL layer and the LSL layer forms a compressive stress acting in the USL layer and a tensile stress acting on the LSL layer , The stress acting on the laminate formed by the USL layer and the LSL layer (may be referred to herein as the "USL / LSL structure") causes a distortion upwardly convex in the opposite direction the above-mentioned delay, which is caused by the difference in the thermal expansion coefficient. Accordingly, the US L / LSL structure can efficiently reduce the warpage of the wafer.
    In this case, the stress acts on the USL / LSL structure, with the fulcrum near the interface between the USL layer and the LSL layer. *** " Layer is located. It is believed that the fulcrum has a width (with a thickness in the growth direction) of about several to several tens of nanometers, because in reality the crystal has dislocations and uneven interfaces. When the GaN crystal contains many impurity atoms such as carbon atoms, the GaN crystal easily forms defects near the interfaces between the stacked layers. Therefore, if the USL / LSL structure contains many impurities, it is believed that many defects are formed at the interface between the USL layer and the LSL layer or at the superlattice interfaces between the USL layer and the LSL layer. When forces act on such interfaces with many defects, it is believed that crystallization relaxation occurs near the crystal interfaces. The crystallization relaxation absorbs the stress formed in the USL / LSL structure and the stress formed in the USL / LSL structure no longer contributes to upward convex distortion. In other words, the USL / LSL structure no longer controls the amount of warpage of the wafer. Accordingly, a semiconductor wafer containing many carbon atoms is affected only by the force resulting from the difference in thermal expansion coefficient between Si and GaN, and thus significantly convexly warped downward.
    To address this problem, the semiconductor wafer 100 relating to the present embodiment has a connection layer 120 between the first superlattice layer 110 (equivalent to the LSL layer described above) and the second superlattice layer 130 (equivalent to that described above USL layer). The connection layer 120 serves as the fulcrum of the stress formed by the difference in average lattice constant between the first superlattice layer 110 and the second superlattice layer 130. The bonding layer 120 is thicker than the first layer 112, the second layer 114, the third layer 132, and the fourth layer 134 forming the first superlattice layer 110 and the second superlattice layer 130, and has a low density of interfaces per unit length in the growth direction (the thickness direction) on. Thus, the tie layer 120 is less likely to be affected by the relaxation at the interfaces. Accordingly, even if the first superlattice layer 110 or the second superlattice layer 130 contains many carbon atoms, the connection layer 120 allows the stress in the first superlattice layer 110 to be refracted / 33 .12 * ··· ···· ··
    and the voltage formed in the second superlattice layer 130 is mutually transmitted. That is to say, the extent of the delay can be controlled. As a result, the warpage of the semiconductor wafer 100 can be reduced.
    In addition, since the interconnection layer 120 is thicker than the first layer 112, the second layer 114, the third layer 132, and the fourth layer 134 constituting the first superlattice layer 110 and the second superlattice layer 130, the interconnection layer 120 also effectively decreases during their growth the defects, such as dislocations, which are formed at the interfaces. The reason is the fact that dislocations having opposite-sign burger vectors are combined together as they grow. As a result, the bonding layer 120 can contribute to the reduction of defects not only at the interfaces but also in the bulk crystals. Thus, it is believed that the interconnect layer 120 may allow the stress to be transferred more effectively. For the reasons described above, even if the first superlattice layer 110 or the second superlattice layer 130 has a high concentration of carbon atoms, the warpage of the wafer can be reduced.
    The above-described semiconductor wafer 100 can be manufactured by the following manufacturing method. The buffer layer 104 is formed on the carrier wafer 102. Thereafter, the first unit layer 116 is formed "times" to form the first superlattice layer 110. Here, the first unit layer 116 is composed of the first layer 112 and the second layer 114. Thereafter, the connection layer 120 is formed, and the second unit layer 136 is formed m-fold to form the second superlattice layer 130. Here, the second unit layer 136 is composed of the third layer 132 and the fourth layer 134. In addition, the nitride semiconductor crystal layer 140 may be formed. Here, during one or more films selected from forming the first superlattice layer 110 and forming the second superlattice layer 130, one or more of the layers 110 and 130 are formed such that the layers contain impurities that enhance the breakdown voltage of the layers and the ones higher concentration than 7 x 10 18 [atoms / cm 3 ].
    The first layer 112, the second layer 114, the interconnect layer 120, the third layer 132, the fourth layer 134, and the nitride semiconductor crystal layer 140 may be separated by / 33 • ····················. · · · ·
    · * · · · · · · ··· ···· · · · · · · · epitaxial growth. The epitaxial growth can be realized using, for example, MOCVD (Metal Organic Chemical Vapor Deposition) and MBE (Molecular Beam Epitaxy). When MOCVD is used, the source gas may be trimethylgallium (TMG), trimethylaluminum (TMA) or NH3 (ammonia). The carrier gas may be a nitrogen or hydrogen gas. The reaction temperature can be selected in the range of 400 ° C to 1300 ° C.
    When carbon atoms are used as impurities, the concentration of the carbon atoms can be controlled by adjusting at least one of the ratio between the Group III source gas and the Group V source gas, the reaction temperature and the reaction pressure. Provided the other conditions are the same, the concentration of carbon atoms decreases as the reaction temperature increases and increases as the ratio of the Group V source gas to the Group III source gas decreases. In addition, the concentration of carbon atoms increases as the reaction pressure decreases. The concentration of carbon atoms can be determined, for example, by SIMS (secondary ion mass spectrometry).
    Depending on the composition and thickness of the nitride semiconductor crystal layer 140, one or more parameters selected from (i) the composition of each of the first to fourth layers 112 to 134, (ii) the thickness of each of the first to fourth layers 112 to 134 (iii) the number n of the unit layers contained in the first superlattice layer 110 and (iv) the number m of the unit layers contained in the second superlattice layer 130 are adjusted so that the warpage of the semiconductor wafer 100 is measured on the surface of the nitride semiconductor crystal layer 140 is 50 pm or less. Depending on the composition and the thickness of the nitride semiconductor crystal layer 140, the number n of the unit layers contained in the first superlattice layer 110 and the number m of the unit layers contained in the second superlattice layer 130 may be set so that the distortion of the semiconductor wafer 100 measured at the surface of the nitride semiconductor crystal layer 140 is 50 pm or less.
    / 33 • · · · • * • · • · ·· • ·
    • First Embodiment [0033]
    A 10,4 cm (4 inch) Si wafer (having a thickness of 625 pm, p-doped) with the plane orientation (111) was used as the carrier wafer 102, and an A1N layer having a thickness of 150 nm was deposited on the Si wafer is formed as the buffer layer 104. On this A1N layer, an A1N layer having a thickness of 5 nm was formed as the first layer 112, and an AlojsGao.ssN layer having a thickness of 16 nm was formed as the second layer 114. The A1N layer with a thickness of 5 nm and the Alo.isGao ^ sN layer form the first unit layer 116. Here, 75 first unit layers were formed to provide the first superlattice layer 110. Thereafter, an A1N layer having a thickness of 70 nm was formed as the connection layer 120. In addition, an A1N layer having a thickness of 5 nm was formed as the third layer 132, and an Alo.iGao.N layer having a thickness of 16 nm was formed as the fourth layer 134. The A1N layer with a thickness of 5 nm and the AlopGa ^ N provide the second unit layer 136. Here, 75 second unit layers 136 were formed to provide the second superlattice layer 130. Thereafter, a GaN layer having a thickness of 800 nm was formed as a base layer of the device 142, and an Alo, 2Gao, 8N layer having a thickness of 20 nm was formed as the active layer 144. It should be noted that a plurality of types of semiconductor wafers 100 were fabricated with the reaction temperature set to different values during formation of the first superlattice layer 110. In this way, a plurality of semiconductor wafers 100 having five different levels of the concentration of carbon atoms, ie, 1 x 10 18 , 5 x 10 18 , 7 x 10 18 , 1 x 10 19, and 6 x 10 (in cm ') were prepared. The average lattice constant of the first superlattice layer 110 is 0.316187 nm, and the average lattice constant of the second superlattice layer 130 is 0.316480 nm. The mean lattice constant of the connection layer 120 is 0.311200 nm.
    (Comparative Examples)
    To compare with the embodiments, the following first to third comparative examples were prepared.
    [First Comparative Example]: The bonding layer 120 was not provided, the Al ratio of the fourth layer 134 was set to 0.15, so that the mean lattice constant of the first superlattice layer 110 was set to be equal to / 33.
    Is the average lattice constant of the second superlattice layer 130, and the other properties were the same as those in the first embodiment.
    [Second Comparative Example]: The Al ratio of the fourth layer 134 was set to 0.15, so that the mean lattice constant of the first superlattice layer 110 was set to be equal to the mean lattice constant of the second superlattice layer 130, and the other properties were same as in the first execution.
    [Third Comparative Example]: The bonding layer 120 was not provided, and the other properties were the same as in the first embodiment.
    Fig. 2 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for the semiconductor wafers of the first embodiment. Fig. 3 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for the semiconductor wafers of the first comparative example. 4 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for the semiconductor wafers of the second comparative example. Fig. 5 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for the semiconductor wafer of the third comparative example. The concentration of carbon atoms means the mean concentration, measured by SIMS depth analysis. The amount of distortion was evaluated by measuring the height of the respective parts of the wafer with laser light. It should be noted that the warpage takes a positive value when measured in the direction in which the center part of the wafer is higher than the edge part of the wafer. In order to determine the breakdown voltage, the current and the voltage between the ohmic electrode of 250 pm x 200 pm formed on the active layer 144 and the ohmic electrode formed on the entire back plane of the carrier wafer 102 were measured. Here, the breakdown voltage has been defined as the voltage applied when the current exceeds 1 pA / mm 2 .
    The results shown in Figs. 2 to 5 indicate that the breakdown voltage increases to about 700 V in the region where the concentration of carbon atoms exceeds 5 x 10 (cm '). In the first to third comparative examples, however, the / 33 ······· ··· * · · 1 t ····· ··· ··· 1 exceeds ··· ·· ·· ·
    On the other hand, in the first embodiment, the amount of distortion is about 40 gm or less, even if the concentration of carbon atoms is high. Thus, the extent of the delay can be kept small. It should be noted that in the area where the io o
    Concentration of the carbon atoms is low and 5x10 (cm ') or less, the second and third comparative examples also keep the amount of distortion to a similar extent small as the first embodiment. It is believed that this is achieved by the effect of the interconnection layer 120 (the second comparative example) and the effect of the difference in average lattice constant between the first superlattice layer 110 and the second superlattice layer 130 (the third comparative example). However, the advantageous effects achieved by the second and third comparative examples are limited to the range in which the concentration of the carbon atoms is low, and are lost in the region where the concentration of the carbon atoms is high.
    Second Embodiment
    According to a second embodiment, a semiconductor wafer was prepared in the same manner as in the first embodiment except that the composition of the interconnection layer 120 is continuously varied in the thickness direction from the first superlattice layer 110 to the second superlattice layer 130 from A1N to Alo ^ GaojN. Here, the concentration of carbon atoms was set at two different levels of 1 x 10 19 and 6 x 10 19 (in cm ' 3 ). Fig. 6 is a graph showing the amount of distortion and the breakdown voltage with respect to the concentration of carbon atoms for the semiconductor wafers of the second embodiment. Fig. 7 is provided to easily understand the comparison between the first and second embodiments. Fig. 7 is a graph showing the amount of distortion with respect to the concentration of carbon atoms for the semiconductor wafers of the first and second embodiments (II and 12) and the first to third comparative examples (CE1, CE2 and CE3). The results in FIG. 7 indicate that the amount of distortion for the semiconductor wafers of the second embodiment is adjusted not only smaller than the amount of distortion for the semiconductor wafers of the first to third comparative examples but also as the amount of distortion for the semiconductor wafers of FIGS first execution.
    / 33 (third embodiment)
    In a third embodiment, illustrative semiconductor wafers have been fabricated with the numbers n and m set to different values, n being the number of first unit layers 116 in the superlattice layer 110 and the number m being the number of second unit layers 136 in the second superlattice layer 130 denotes. The semiconductor wafers were prepared in the same manner as in the first embodiment except that the concentration of carbon atoms was set to 1 × 10 19 (cm -3 ) and the numbers m and n were set to different values. The numbers n and m were set to three different values of n / m = 75/75, 100/50 and 1/149. Fig. 8 is a graph showing the amount of distortion and the breakdown voltage for the semiconductor wafers of the third embodiment. The results shown in Fig. 8 show that the amount of distortion can be controlled by varying the numbers n and m.
    (Fourth Embodiment)
    In semiconductor wafers of a fourth embodiment, a blue corundum wafer was used as the carrier wafer 102. The semiconductor wafers were produced in the same manner as in the first embodiment, except that a blue corundum wafer was used as the carrier wafer 102, the concentration of carbon atoms was set to 1 x 10 19 (cm ' 3 ), and the numbers n and m were set to different levels were set. The numbers n and m were set at two different levels of n / m = 75/75 and 50/100. Fig. 9 is a graph showing the amount of distortion for the semiconductor wafers of the fourth embodiment. The results shown in FIG. 9 show that the amount of distortion can be controlled by varying the numbers n and m of the unit layers included in the first grid layer 110 and the second superlattice layer 130, even if the carrier wafer 102 is a blue corundum wafer.
    (Fifth Embodiment)
    In a fifth embodiment, illustrative semiconductor wafers were made wherein the Al ratio of the Alga layer, which is the fourth layer 134, was varied in the range of 0.15 to 0.10. The fifth embodiment is the same as the first embodiment, except that the concentration of carbon atoms has been set at 1 x 10 19 (cm -3 ). The Al ratio was set at six different levels of 0.15, 0.14, 0.13, 0.12, 0.11 and 0.10. When the Al ratio has been set at the levels 0.10 and 0.15, respectively, which is one of the cases of the first embodiment and one of the cases of the second comparative example in which the / 33 • · · -, ♦> ····· ············ 1 <5 ·········································
    Concentration of the carbon atoms was 1 x 10 19 (cm ' 3 ), corresponded. Thus, the semiconductor wafers of the first embodiment and the second comparative example, respectively, for which the concentration of carbon atoms was set to 1 x 10 19 (cm ' 3 ) were used as the semiconductor wafers of the fifth embodiment, for which the Al ratio was at levels 0, 10 and 0.15 has been set. When the Al ratio is set to 0.15, 0.14, 0.13, 0.12, 0.11, and 0.10, the average lattice constant of the second superlattice layer 130 takes values of 0.316187, 0.316245, 0 , 316304, 0.316363, 0.316421 and 0.316480 (in nm). Since the mean lattice constant of the first superlattice layer 110 is 0.316187 nm, the difference in the mean lattice constant (the mean lattice constant of the second overlayer 130 - the mean lattice constant of the first overlayer 110) is 0.000000, 0.000059, 0.000117, 0.000176, 0.000235 and 0.000293 (in nm) when the Al ratio is set to 0.15, 0.14, 0.13, 0.12, 0.11 and 0.10.
    Fig. 10 is a graph showing the amount of distortion with respect to the difference in average lattice constant for the semiconductor wafers of the fifth embodiment. The results shown in Fig. 10 show that the amount of distortion decreases as the difference of average lattice constant increases. The results also show that if the average lattice constant of the second overlay 130 becomes only slightly larger than the average lattice constant of the first superlattice layer 110 (as the difference in mean lattice constant becomes larger), the amount of distortion changes and the change in the value of the lattice Scope of the delay is sensitive to the change in the difference of the average lattice constant. This demonstrates that the mechanism described above, which allows the amount of distortion of the semiconductor wafer to be reduced regardless of the introduction of a high concentration of impurities, is effective in controlling the amount of distortion as a result of sufficient mutual transfer of voltage between the first superlattice layer 110 and the second superlattice layer 130 functions.
    Comparing the increase in the difference in the average lattice constant, the decrease in the amount of distortion tends to be saturated after the difference in average lattice constant substantially exceeds 0.00017 nm. This may show such an inclination that the stress begins to increase at the crystal interfaces as a result of the increase in the difference in average lattice constant and lattice relaxation. The increase in the lattice relaxation results in an absorption of the stress, which reduces the controllability of the amount of distortion. Accordingly, it is considered that an upper limit is placed on the range of the difference in average lattice constant to ensure the controllability of the amount of distortion. It should be noted that the facts that the amount of distortion can be accurately controlled by adjusting the difference in the average lattice constant, and that the decrease in the amount of distortion tends to saturate when the difference of the average lattice constant becomes large with the earlier specific mechanism and is concluded on the effectiveness of the mechanism among other facts.
    Explanation of Reference Numerals 100 ... semiconductor wafer, 102 ... carrier layer, 104 ... buffer layer, 110 ... first
    Superlattice layer, 112 ... first layer, 114 ... second layer, 116 ... first unit layer,
    120 .. connecting layer, 130 ... second superlattice layer, 132 ... third layer, 134 ... fourth
    Layer, 136 ... second unit layer, 140 ... nitride semiconductor crystal layer,
    142 .. basic layer of the device, 144 .. .active layer
    权利要求:
    Claims (14)
    [1]
    A semiconductor wafer comprising a carrier wafer, a first superlattice layer, a connection layer, a second superlattice layer and a nitride semiconductor crystal layer, wherein the carrier wafer, the first superlattice layer, the interconnection layer, the second superlattice layer and the nitride semiconductor crystal layer are arranged in an order of the carrier wafer, the first Superlattice layer, the interconnection layer, the second superlattice layer and the nitride semiconductor crystal layer are arranged, the first superlattice layer includes a plurality of first unit layers, each of which is composed of a first layer and a second layer, the second superlattice layer includes a plurality of second unit layers, each of which is composed of a third layer and a fourth layer, the first layer of Al x i Gaai x x N (0 <xl <1), the second layer of Al y i GaI. y iN (0 <yl <1, xl> yl) is formed, the third layer of Al X 2Gai. X 2N (0 <x2 <1), the fourth layer consists of Al ^ Gai.j ^ N (0 <y2 <1, x2> y2), an average lattice constant of the first superlattice layer is different from a mean lattice constant of the second superlattice layer , one or more layers selected from the first superlattice layer and the second superlattice layer, contain impurities that improve a breakdown voltage and have a concentration of more than 7 x 10 18 [atoms / cm 3 ].
    [2]
    2. The semiconductor wafer of claim 1, wherein the foreign atoms comprise one or more species selected from the group consisting of CAtoms, Fe atoms, Mn atoms, Mg atoms, V atoms, Cr atoms, Be atoms and B atoms. Atoms, are.
    [3]
    The semiconductor wafer according to claim 2, wherein the impurity atoms are C atoms or Fe atoms.
    21/33 • · · • ·
    [4]
    The semiconductor wafer according to any one of claims 1 to 3, wherein the compound layer is a crystal layer in contact with the first superlattice layer and the second superlattice layer.
    [5]
    The semiconductor wafer according to any one of claims 1 to 4, wherein a composition of the compound layer changes continuously in a thickness direction of the interconnection layer from the first superlattice layer to the second superlattice layer.
    [6]
    The semiconductor wafer according to any one of claims 1 to 4, wherein a compound layer composition gradually changes in a thickness direction of the interconnection layer from the first superlattice layer to the second superlattice layer.
    [7]
    7. The semiconductor wafer according to any one of claims 1 to 6, wherein the compound layer of Al z Gai_ z N (0 <z <1) is formed.
    [8]
    8. The semiconductor wafer according to claim 1, wherein a thickness of the compound layer is larger than a thickness of each of the first layer, the second layer, the third layer, and the fourth layer.
    [9]
    The semiconductor wafer according to any one of claims 1 to 8, wherein an average lattice constant of the compound layer is smaller than an average lattice constant of each first superlattice layer and second superlattice layer.
    [10]
    The semiconductor wafer according to any one of claims 1 to 9, wherein the first superlattice layer includes 1 to 200 first unit layers each of which is composed of the first layer and the second layer.
    [11]
    The semiconductor wafer according to any one of claims 1 to 10, wherein the second superlattice layer includes 1 to 200 second unit layers each of which is composed of the third layer and the fourth layer.
    22/33 • ·
    [12]
    A method of manufacturing the semiconductor wafer according to any one of claims 1 to 11, wherein the method comprises:
    forming the first superlattice layer by forming the first unit layer composed of the first layer and the second layer,
    Forming the tie layer;
    m-fold forming the second superlattice layer by forming the second unit layer composed of the third layer and the fourth layer; and
    Forming the nitride semiconductor crystal layer, wherein during the one or multiple forming selected from forming the first superlattice layer and forming the second superlattice layer, one or more of the first superlattice layer and the second superlattice layer are formed to contain impurities improve a breakdown voltage of the one or more of the first superlattice layer and the second superlattice layer and having a concentration of more than 7 x 10 14 * * * 18 [atoms / cm 3 ].
    [13]
    13. The method of claim 12, wherein, depending on a composition and a thickness of the nitride semiconductor crystal layer, one or more parameters selected from (i) a composition of each first to fourth layer, (ii) a thickness of each first to fourth layer, (iii) adjusting the number n of unit layers contained in the first superlattice layer; and (iv) setting the number m of the unit layers included in the second superlattice layer so that the warpage of the semiconductor wafer measured on a surface of the nitride semiconductor crystal layer is 50 μm or less.
    [14]
    14. The method according to claim 13, wherein, depending on the composition and the thickness of the nitride semiconductor crystal layer
    The number n of the unit layers included in the first superlattice layer and the number m of the unit layers included in the second superlattice layer are set so that the warpage of the semiconductor wafer measured at the surface of the nitride semiconductor crystal layer is 50 μm or less.
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